In radio frequency zero-IF receivers, DC voltage offsets can seriously degrade the bit error rate (BER) performance of received information. In the context of zero-IF receivers, DC offsets refer to undesired DC voltages that appear in the in-phase (I) and quadrature phase (Q) baseband stages of the receiver, and consequently degrade the performance of the receiver. Two types of DC offsets occur in zero IF receivers. The static type of DC offset may occur in any zero IF receiver, and dynamic DC offsets are unique to zero IF receivers used in TDMA systems. With the trend toward reducing the size of base station receiver circuitry and components through integrated circuitry (IC) design, controlling the static and dynamic DC offsets through conventional methods becomes increasingly difficult.
Static offsets can result from offset voltages inherent to baseband amplifiers and can also result from local oscillator (LO) leakage into the mixers of the IF stages of the receiver. LO leakage can be the result of conducted and/or radiated energy from the local oscillator. For example, LO signals can radiate into IF amplifier traces, couple into the IF stage via power supply circuitry or conduct back through the mixer itself. Therefore, the local oscillator frequency may appear on the input of the IF/LO mixer resulting in the offsets. The static DC offsets are typically corrected by adding AC coupling capacitors to the baseband amplifier stages. The AC coupling capacitors are typically discrete components. Alternatively, offset compensation loops, as known in the art, are placed throughout the devices. In both cases, the effect is to add a high pass filter response to the baseband filter function. In some TDMA cellular systems, such as the GSM systems, the baseband information spectrum can extend down to zero Hz. Consequently, any high pass filtering will result in lost information in such systems. However, by keeping the high pass corner frequency below about 40 Hz, BER degradation can be kept below an acceptable level.
The dynamic type of DC offsets are more critical in zero IF baseband receivers. Dynamic offsets result from the same LO leakage described with respect to the static DC offsets. However, in the case of TDMA receivers, the LO leakage signal which appears at the RF port of the mixer can vary from timeslot to timeslot, producing a DC offset waveform at the output of the receiver as shown in FIG. 1. As shown, the desired I or Q channel information waveform rides on top of the dynamic DC offset waveform. Consequently, from the perspective of any individual timeslot (TS0-TS7), there is a non zero DC offset above or below the 0 VDC reference voltage. Although AC coupled, the receiver typically has no way to reject this waveform. For example, a GSM type cellular TDMA system has a timeslot duration of approximately 600 microseconds. The generated dynamic DC offset waveform may have an effective frequency of less than 1 KHz. This waveform easily passes through the typical 90 KHz low pass filter response of the GSM baseband stages.
The magnitude and phase of the LO vestige signals present at an RF port of the mixer is a function of gains and reflection coefficients throughout the IF portion of the receiver. In TDMA systems, the very same gains and reflection coefficients can change dramatically as a receiver reconfigures its gain (AGC) setting between timeslots. The problem is compounded by the fact that the gain settings for a given timeslot are also time variant as the mobile transmitting units move closer and further from the base station and as call traffic comes and goes. Therefore, the dynamic DC offset wave not only changes from timeslot to timeslot, but also from frame to frame. The presence of dynamic DC offset voltages as visible to a detector stage of a receiver has been shown to degrade BER performance. For example, it has been found, that a zero IF TDMA base station receiver should have a combined I channel DC offset and Q channel DC offset of less than 3% of the full scale input of an A/D converter that converts the analog signal to digital signal for the detector. With the combined DC offsets of the I and Q channel less than 3%, the DC offset can produce less than 0.5 dB degradation of BER performance, hence, it would be desirable to remove or substantially reduce the undesirable dynamic DC offset prior to channel equalization to reduce BER.
Conventional DC offset correction methods generally include placing the LO signal trace on one side of a circuit board and placing the IF signal trace on another side of the PC board to help reduce the radiation impact of the signals. In addition, metal shielding is typically placed around the LO to further help isolate the LO radiation from interfering with other receiver circuitry. Such methods can not typically be applied to integrated circuits due to the small size and location of the signal traces on the IC and other factors, particularly when the quadrature down converter and baseband circuitry is on one integrated circuit.
Another method of reducing DC offsets is to lower the IF frequency prior to the baseband stage through a triple conversion receiver where three IF stages (including the baseband stage) are used and the IF stage prior to the baseband stage has a lower LO frequency because it has been scaled down. In this way, the LO signal may be at a lower frequency thereby being less prone to radiation, which in turn causes less offset. However, the use of triple conversion filters requires additional components on an integrated circuit and adds complexity resulting in higher costs.
Also, another type of offset correction circuit, disclosed in U.S. Pat. No. 5,442,655 to Dedic et al., issued Aug. 15, 1995 tends to first eliminate all DC offset components both natural offsets and undesired offsets. Natural DC offset refers to the inherent, non-zero, DC value of the burst or timeslot. It has been found that with random modulation, there is greater than 40% probability that the natural DC offset (of I or Q) will exceed 1.5% of full scale. To remove the natural offset would have the same degradation affects as adding an erroneous offset of equal amplitude. The Dedic et al. circuit then attempts to estimate the natural offset from received data and add the natural offset back in to the data. By estimating the natural offset, error can be unnecessarily introduced. A viable DC offset solution should have the ability to distinguish between the natural DC offsets, and the undesired DC offsets, and remove only the undesired term.
In addition, anther type of offset correction technique is disclosed in U.S. Pat. No. 5,422,889 to Sevenhans et al., issued Jun. 6, 1995 and titled "Offset Correction Circuit." This technique attempts to correct for DC offset by continuously updating different variable parameter offset correction values for different carrier frequencies stored in a memory. However, the Sevenhans et al. receiver is a DC coupled direct conversion receiver that can potentially suffer from saturation of baseband amplifiers due to static DC offsets. An offset correction value is calculated and applied in an attempt to keep DC offsets within some specified boundary. A more suitable approach would be desirable for AC coupled baseband receivers where DC offsets should be substantially eliminated.
Therefore, there exists a need for a cellular TDMA base station receiver that has DC offset correction suitable for use in a integrated circuit receiver. Also, it would be desirable if the base station receiver with dynamic DC offset correction also eliminated or reduced BER degradation by substantially removing only the undesired DC offset component.